1. Field of the Invention
The present invention relates to multiport memory devices, and more particularly, to an improvement of operation when accesses to the same memory cell are in contention.
2. Description of the Background Art
A multiport memory is a memory having a plurality of ports, and is, used for example, as a register file contained in a microprocessor and the like. A port here is a series of circuits which operates with an address signal.
(The First Prior Art)
FIG. 16 is a schematic diagram of a circuit showing an example of a conventional multiport memory. The multiport memory of this type is disclosed in Japanese Patent Laying-Open No. 63-201986.
Referring to FIG. 16, a memory cell array includes a plurality of 2-port memory cells disposed in an array of a plurality of rows and a plurality of columns. In FIG. 16, only one memory cell MC0 is shown. A plurality of first and second word lines WL1, WL2 are arranged corresponding to a plurality of rows of the memory cell, while a plurality of first and second bit lines BL1, BL2 are arranged corresponding to a plurality of columns of the memory cell. A memory cell MC is connected to corresponding first and second word lines WL1, WL2 and corresponding first and second bit lines BL1, BL2.
A first address decoder 21 decodes an externally applied first signal A1 to select one of a plurality of first word lines WL1. A first word line driving circuit 31 drives the selected first word line WL1 in response to an output of the first address decoder 21. A second address decoder 22 selects one of a plurality of second word lines WL2 in response to an externally applied second address signal A2. A second word line driving circuit 32 drives the selected second word line WL2 in response to an output of the second address decoder 22.
Data is read from a plurality of memory cells MC connected to the driven first word line WL1 to the respective corresponding first bit line BL1. Data is also read from a plurality of memory cells MC connected to the driven second word line WL2 to the respective corresponding second bit line BL2.
In the read operation, a sense amplifier 5 amplifies data on a plurality of first bit lines BL1 and data on a plurality of second bit lines BL2 to provide those data to first and second data buses D1, D2.
A write driver & write control circuit 6 provides, in the write operation, data on first and second data buses D1, D2 to a plurality of first and second bit lines BL1, BL2, respectively. A bit line precharge circuit 7 precharges first and second bit lines BL1, BL2.
An operation control circuit 8 receives first and second reference clocks .phi.1, .phi.2, a chip selecting signal CS, and first and second read/write signals RW1, RW2 to generate precharge signals P1, P2, P3, first and second sense enable signals SE1, SE2, and first and second write enable signals WE1, WE2.
The precharge signals P1, P2, P3 are applied to the bit line precharge circuit 7. The first and second sense enable signal SE1, SE2 are applied to the sense amplifier 5. The first and second write enable signals WE1, WE2 are applied to the first word line driving circuit 31, the second word line driving circuit 32, and the write driver & write control circuit 6.
The chip selecting signal CS is a control signal for selecting between a selected state and a non-selected state of the multiport memory. The first read/write signal RW1 is a control signal for selecting a read state or a write state with regard to a first port, while the second read/write signal RW2 is a control signal for selecting a read state or a write state with regard to a second port.
The precharge signal P1 is a control signal for precharging the first bit line BL1, the precharge signal P2 is a control signal for precharging the second bit line BL2, and the precharge signal P3 is a control signal for equalizing potentials of the first and second bit lines BL1, BL2 in order to precharge the first and second bit lines BL1, BL2 at high speed.
The first sense enable signal SE1 is a signal for activating a sense operation of data on the first bit line BL1. The second sense enable signal SE2 is a signal for activating a sense operation of data on the second bit line BL2. The first write enable signal WE1 is a control signal for setting the first port to a write state or a read state. The second write enable signal WE2 is a control signal for setting the second port to the write state or the read state.
When the first write enable signal WE1 is at a logic high or "H" level and at a logic low or "L" level, the first port is set to the write state and the read state, respectively. When the second write enable signal WE2 is at "H" and at "L", the second port is set to the write state and the read state, respectively.
The write driver & write control circuit 6 transfers data on the first data bus D1 to the first and second bit lines BL1, BL2 as write data when the first write enable signal WE1 is at "H". The write driver & write control circuit 6 also transfers data on the second data bus D2 to the first and second bit lines BL1, BL2 as write data when the second write enable signal WE2 is at "H". When the first and second write enable signals WE1, WE2 are at "L", the write driver & write control circuit 6 attains a high impedance state.
FIG. 17 is a schematic diagram of a circuit showing a configuration of a 2-port memory cell MC0.
The memory cell MC0 includes inverters G1, G2 and first and second access gates T1, T2 configured of N channel MOS transistors. The input terminal of the inverter G1 and the output terminal of the inverter G2 are connected to a storage node Q1. The output terminal of the inverter G1 and the input terminal of the inverter G2 are connected to a storage node Q2, thereby configuring a storage retaining circuit.
The first access gate T1, connected between the storage node Q1 and the first bit line BL1, receives a potential of the first word line WL1 to be rendered conductive or non-conductive. The second access gate T2, connected between the storage node Q2 and the second bit line BL2, receives a potential of the second word line WL2 to be rendered conductive or non-conductive.
The inverters G1, G2 configure a flip-flop, and data complementary to each other are stored in the storage nodes Q1, Q2.
If the first word line WL1 is selected in the read operation, the first access gate T1 is turned on to cause data retained in the storage node Q1 to be transferred to the first bit line BL1. The data is provided to the first data bus D1 through the sense amplifier 5 shown in FIG. 16. If the second word line WL2 is selected, the second access gate T2 is turned on to cause data retained in the storage node Q2 to be transferred to the second bit line BL2. The data is provided to the second data bus D2 through the sense amplifier 5 shown in FIG. 16.
Both first and second bit lines BL1, BL2 are used in the write operation. Data on the first or second data buses D1, D2 shown in FIG. 16 are provided to the first and second bit lines BL1, BL2 through the write driver & write control circuit 6. Write data and inverted data of the write data are provided to the first bit line BL1 and the second bit line BL2, respectively. If the first and second word lines WL1, WL2 are selected, the first and second access gates T1, T2 are turned on, the write data on the first bit line BL1 is written in the storage node Q1, and the inverted data on the second bit line BL2 is written in the storage node Q2.
FIG. 18 is a schematic diagram of a circuit showing an example of configuration of first and second address decoders 21, 22 and first and second word line driving circuits 31, 32. In FIG. 18, only a portion corresponding to a set of the first and second word lines WL1, WL2 is shown.
An NAND gate G21 and an NAND gate G22 are included in the first address decoder 21 and the second address decoder 22, respectively. Tristate buffers G31a, G31b and a control signal generating circuit 81 are included in the first word line driving circuit 31. Tristate buffers G32a, G32b and a control signal generating circuit 82 are included in the second word line driving circuit 32.
Each bit of the first address signal A1 or an inverted signal thereof is provided to each input terminal of the NAND gate G21. When an output of the NAND gate G21 attains "L", the first and second word lines WL1, WL2 are selected. Each bit of the second address signal A2 or an inverted signal thereof is provided to each input terminal of the NAND gate G22. When an output of the NAND gate G22 attains "L", the first and second word lines WL1, WL2 are selected.
The tristate buffer G31a is activated in the read operation or the write operation with regard to the first port. The tristate buffer G31b is activated only in the write operation with regard to the first port. The tristate buffer G32a is activated in the read operation or the write operation with regard to the second port. The tristate buffer G32b is activated only in the write operation with regard to the second port.
The control signal generating circuit 81 controls the tristate buffers G31a, G31b in response to the first and second write enable signals WE1, WE2. The control signal generating circuit 82 controls the tristate buffers G32a, G32b in response to the first and second write enable signals WE1, WE2.
If the first write enable signal WE1 is at "L" (the first port is at the read state), the tristate buffer G31a drives the first word line WL1 to "H" to cause an output of the tristate buffer G31b to attain a high impedance state. If the second write enable signal WE2 is at "L" (the second port is at the read state), the tristate buffer G32a drives the second word line WL2 to "H" to cause an output of the tristate buffer G32b to attain a high impedance state.
If the first write enable signal WE1 is at "H" (the first port is at the write state), the first and second word lines WL1, WL2 are driven to "H" by the tristate buffers G31a, G31b, respectively. At that time, the outputs of the tristate buffers G32a, G32b both attain the high impedance states in order to inhibit a selecting operation in the second port.
If the second write enable signal WE2 is at "H" (the second port is at the write state), the second and first word lines WL2, WL1 are driven to "H" by the tristate buffers G32a, G32b, respectively. At that time, the outputs of the tristate buffers G31a, G31b both attain the high impedance states in order to inhibit a selecting operation in the first port.
(The Second Prior Art)
FIG. 19 is a block diagram showing another example of a conventional multiport memory. The multiport memory of this type is disclosed in Japanese Patent Laying-Open No. 62-175993.
Referring to FIG. 19, a memory cell array 10 includes a plurality of 2-port memory cells disposed in a matrix of a plurality of rows and a plurality of columns. A first row address decoder 21 selects any one of a plurality of rows in the memory cell array 10 in response to a first row address signal A1r. A second row address decoder 22 selects any one of a plurality of rows in the memory cell array 10 in response to a second row address signal A2r. A first column address decoder 41 selects any one of a plurality of columns in the memory cell array 10 in response to a first column address signal A1c. A second column address decoder 42 selects any one of a plurality of columns in the memory cell array 10 in response to a second column address signal A2c.
A first input/output circuit 91 reads data to the first data bus D1 from a memory cell selected by the first row address decoder 21 and the first column address decoder 41, or writes data on the first data bus D1 in a memory cell selected by the first row address decoder 21 and the first column address decoder 41, in response to a read/write signal RW1.
A second input/output circuit 92 reads data to the second data bus D2 from a memory cell selected by the second row address decoder 22 and the second column address decoder 42, or writes data on the second data bus D2 in a memory cell selected by the second row address decoder 22 and the second column address decoder 42, in response to a read/write signal RW2.
A BUSY circuit 100 generates first and second busy signals BUSY1, BUSY2 in response to the first and second row address signals A1r, A2r, the first and second column address signals A1c, A2c, and the first and second read/write signals RW1, RW2.
The first row address signal A1r and the first column address signal A1c configure a first address signal A1 corresponding to the first port, and the second row address signal A2r and the second column address signal A2c configure a second address signal A2 corresponding to the second port.
FIG. 20 is a diagram showing a configuration of a 2-port memory cell. The memory cell MC1 of this type is a flip-flop type static memory cell.
The memory cell MC1 includes a flip-flop circuit FF, first access gates T1a, T1b configured of an N channel MOS transistor, and second access gates T2a, T2b configured of an N channel MOS transistor.
The memory cell MC1 is connected to the first word line WL1 corresponding to the first port, the second word line WL2 corresponding to the second port, the first bit lines BL1a, BL1b corresponding to the first port, and the second bit lines BL2a, BL2b corresponding to the second port.
The first access gate T1a, is connected between the flip-flop circuit FF and the first bit line BL1a to be rendered conductive or non-conductive in response to potential of the first word line WL1. The first access gate T1b is connected between the flip-flop circuit FF and the first bit line Bl1b to be rendered conductive or non-conductive in response to the potential of the first word line WL1. The second access gate T2a is connected between the flip-flop circuit FF and the second bit line BL2a to be rendered conductive or non-conductive in response to the potential of the second word line WL2. The second access gate T2b is connected between the flip-flop circuit FF and the second bit line BL2b to be rendered conductive or non-conductive in response to the potential of the second word line WL2.
Data complementary to each other are provided to the first bit lines BL1a, BL1b. Similarly, data complementary to each other are also provided to the second bit lines BL2a, BL2b. The first and second word lines WL1, WL2 configure a group of word lines. The first and second bit lines BL1a, BL1b, BL2a, BL2b also configure a group of bit lines.
The first row address decoder 21 shown in FIG. 19 decodes the first row address signal A1r to select the first word line WL1 included in any one of a plurality of word line groups. The first column address decoder 41 decodes the first column address signal A1c to select a set of first bit lines BL1a, BL1b included in any one of a plurality of bit line groups.
The second row address decoder 22 decodes the second row address signal A2r to select the second word line WL2 included in any one of a plurality of word line groups. The second column address decoder 42 decodes the second column address signal A2c to select a set of second bit lines BL2a, BL2b included in any one of a plurality of bit line groups.
Referring to FIG. 20, when the first word line WL1 is selected, the first access gates T1a, T1b are turned on to cause data and an inverted data thereof retained in the flip-flop circuit FF to be read to the first bit lines BL1a, BL1b, respectively, or data and an inverted data thereof on the first bit lines BL1a, BL1bto be written in the flip-flop circuit FF. When the second word line WL2 is selected, the second access gates T2a, T2b are turned on to cause data and an inverted data thereof retained in the flip-flop circuit FF to be read to the second bit lines BL2a, BL2b, respectively, or data or an inverted data thereof on the second bit lines BL2a, BL2b to be written in the flip-flop circuit FF.
Since it is possible to select the first word line WL1 corresponding to the first port and the second word line WL2 corresponding to the second port independently, data can be written in any memory cell from a bit line corresponding to each port independently, or data stored in any memory cell can be read to a bit line corresponding to each port independently.
FIG. 21 is a schematic diagram of a circuit showing a configuration of one part of the BUSY circuit 21. In FIG. 21, only a signal generating circuit for generating the second busy signal BUSY2 is shown.
The signal generating circuit includes a plurality of 2-input exclusive OR circuits G91 and OR circuits G92, G93. Each of the exclusive OR circuits G91 has one input terminal provided with each bit A1 (i) of the first address signal A1, and the other input terminal provided with each bit A2 (i) of the second address signal A2, where i is any integer of 0 to n.
Outputs of the plurality of exclusive OR circuits G91 are provided to the OR circuit G92. The output of the OR circuit G92 is provided to one input terminal of the OR circuit G93. The first read/write signal RW1 is applied to the other input terminal of the OR circuit G93. The second busy signal BUSY2 is provided from the OR circuit G93.
The plurality of exclusive OR circuits G91 and the OR circuit G92 configure an address match/mismatch detecting circuit.
A signal generating circuit for generating the first busy signal BUSY1 also includes an address match/mismatch detecting circuit configured of the plurality of exclusive OR circuits G91 and the OR circuit G92, and the OR circuit G93 for generating the first busy signal BUSY1, as well as a signal generating circuit shown in FIG. 21, but the second read/write signal RW2 is applied to the other input terminal of the OR circuit G93.
The first busy signal BUSY1 is a stop signal for indicating stop of the write operation or the read operation in the first port. The second busy signal BUSY2 is a stop signal for indicating stop of the write operation or the read operation in the second port.
When the first address signal A1 corresponding to the first port and the second address signal A2 corresponding to the second port express exactly the same address, the output of the OR circuit G92 attains "L". At that time, if the first read/write signal RW1 is at "L" (the first port is at the write state), the second busy signal BUSY2 attains "L" in order to avoid writing data in the same memory cell. An external CPU stops access to the second port in response to the second busy signal BUSY2.
Similarly, if the second read/write signal RW2 is at "L" (the second port is at the write state), the first busy signal BUSY1 attains "L" in order to avoid writing data in the same memory cell. The external CPU stops access to the first port in response to the first busy signal BUSY1.
In a multiport memory shown in FIG. 16, since both first and second bit lines BL1, BL2 are used in the write operation, the write operation cannot be carried out in two ports simultaneously. In this case, after the write operation of the port which is accessed earlier is completed, the write operation of the port which is accessed later is carried out. Therefore, it is not possible to write data in the same memory cell from two ports simultaneously. As a result, data stored in the memory cell is protected.
However, when the write operation is being carried out in one port, it is not also possible to carry out the read operation in the other port. It is therefore necessary to carry out the read operation in one port after completion of the write operation in the other, which poses a problem of slow access speed.
In a conventional multiport memory shown in FIG. 19, it is possible to carry out the write operation or the read operation in two ports simultaneously. However, when data is written in the same memory cell from two ports simultaneously, data stored in the memory cell is destroyed.
It is therefore necessary to inform an external circuit such as CPU that when the write of data in a certain memory cell in one port is being carried out, the write of data in the same memory cell in the other port is inhibited, and provision of the BUSY circuit 100 is required for that purpose. As a result, circuits and interconnection are increased.